1. Field of the Invention
The present invention relates to a method of producing a semiconductor device, and particularly relates to a method of producing a semiconductor device having copper (Cu) wiring.
2. Description of the Related Art
Along with a reduction in design rules, a reduction of a wiring capacitance in reduced wiring has been required in an LSI and other semiconductor devices. Thus, copper (Cu) is broadly applied as a wiring material. It is known that when applying Cu wiring, in addition to a reduction of a wiring capacitance, reliability of wiring is also improved.
A semiconductor device wherein buried metal wiring is configured by using the above Cu and a production method thereof will be explained.
FIG. 1 is a sectional view of a semiconductor device wherein buried metal wiring is configured by using Cu.
An interlayer insulation film 101 made by an insulation material, such as a silicon oxide, is formed by covering over a semiconductor substrate 100 formed with a not shown transistor or other semiconductor element, and wiring grooves (101a and 101b) are formed on the interlayer insulation film 101 by a single damascene method or a dual damascene method. In the case of the dual damascene method, it is configured that a contact hole reaching to the semiconductor substrate 100, etc. is provided at the bottom of the wiring groove.
A barrier layer 102 made, for example, by Ta, TaN, TiN, W, WN, etc. is formed so as to cover inner walls of the wiring grooves (101a and 101b), and buried metal wiring (103a and 103b) made by Cu is formed inside thereof so as to bury the wiring grooves (101a and 101b).
A barrier insulation film 104 made by silicon nitride is formed by covering allover the buried metal wiring (103a and 103b) buried in the wiring grooves (101a and 101b), and an upper layer insulation film 105 made by an insulation material, such as a silicon oxide, is formed thereon.
Next, a method of producing a semiconductor device wherein a buried metal wiring is configured by using Cu as above will be explained.
First, as shown in FIG. 2A, an interlayer insulation film 101 is formed by depositing an insulation material, such as a silicon oxide, for example by the Chemical Vapor Deposition (CVD) method so as to cover the semiconductor substrate 100 formed with a not shown transistor or other semiconductor element, and wiring grooves (101a and 101b) are formed on the interlayer insulation film 101 by photolithography processing and etching processing such as Reactive Ion Etching (RIE).
Next, as shown in FIG. 2B, a barrier layer 102 is formed by depositing Ta, TaN, TiN, W, WN, etc. for example by a sputtering method or a CVD method.
Next, successively from the formation of the above barrier layer 102, without exposing in the air, a Cu seed layer is formed by covering allover the barrier layer 102.
Next, the Cu seed layer is grown by electrolytic plating processing so as to form a Cu buried conductive layer 103.
Next, as shown in FIG. 3A, the buried conductive layer 103 is polished from an upper surface, for example, by a Chemical Mechanical Polishing (CMP) method, electrolytic polishing processing or other processing and Cu being outside of the wiring grooves (101a and 101b) is removed so as to obtain buried metal wiring (103a and 103b) buried in the wiring grooves (101a and 101b). At this time, portions of the barrier layer 102 being outside of the wiring grooves (101a and 101b) are also removed.
Next, as shown in FIG. 3B, silicon nitride is deposited, for example, by a sputtering method or a CVD method to form a barrier insulation film 104.
Next, on the barrier insulation film 104, a silicon oxide or other insulation material is deposited, for example, by a CVD method to form an upper layer insulation film 105.
From the above processing, a semiconductor device wherein buried metal wiring is configured by using Cu shown in FIG. 1 can be produced.
In the Cu wiring configured as above, there are disadvantages such that (1) a barrier insulation film of SiN, SiC, etc. having a high dielectric constant is required to suppress diffusion of Cu in a silicon oxide insulation film, and a wiring capacitance is increased due to the barrier insulation film material having a high dielectric constant, and (2) a boundary face between the Cu wiring and the barrier insulation film has low electromigration (EM) resistance.
To prevent the above disadvantages, there is an approach of applying a Cu diffusion prevention material to only on the Cu wiring. Because wiring is a metal material, a method of using a metal material as its cap is widely used.
For example, there is a method of forming a recess of several tens of nm or so at an upper portion of the Cu wiring, forming a film of a barrier metal material of TiN, TiW, etc. allover thereon and leaving a barrier metal film formed on the wiring portion by a CMP method and a method of forming a film selectively on the Cu by a CVD method of W. etc.
Also, a method of forming a film of a Co base material on the Cu wiring by electroless plating may be mentioned as one method. This technique brings advantages of enabling film formation with a simple apparatus, not requiring a plurality of different processes and requiring inexpensive process costs including material costs when compared with the above two techniques.
On the other hand, there are challenges left, such as a difficulty of selective growing on Cu and damages by corrosion on Cu due to a catalyst process included in the electroless plating processing of a Co base material, etc.
Among them, selective growing on Cu has been almost solved by a method of performing light etching on a field by HF, etc. on a base subjected to electroless plating (for example, refer to the article (The 61st Semiconductor Integrated Circuit Symposium Lectures (pp.13 to 18), 2001)).
However, on the other hand, damages by corrosion on Cu in the catalyst process have not been solved yet as described below.
In electroless plating using a catalyst process, palladium (Pd) is widely used as a catalyst substance. The catalyst process is substitutional plating for substituting Pd for Cu as a base, and it is inevitable to etch a part of the Cu as a base.
FIG. 4 is a schematic view for explaining a disadvantage in the above catalyst process (substitutional plating).
The Cu as a base is made by crystal grains and the boundaries are called crystal boundaries 103c. In the catalyst process (substitutional plating), corrosion on the weakly bonded crystal boundaries 103c is notable compared with that on Cu crystal, and not only a surface of the Cu but even inside thereof is sometimes corroded in extreme cases. Due to the corrosion, a corrosion hole is formed on the Cu forming the wiring, namely, a void is formed in the wiring so as to decrease an effective sectional area of the wiring and to remarkably deteriorate reliability of electromigration (EM), etc.
Furthermore, palladium sulfate and palladium chloride, etc. are widely used as a Pd source, and solutions of these have a pH on the strongly acidic side and are in a range where Cu is easily ionized, so that they act as a factor of accelerating the corrosion.